1. Field of the Invention
The present invention relates generally to methods for etching layers within integrated circuits. More particularly, the present invention relates to methods for etching polysilicon layers within integrated circuits.
2. Description of the Related Art
Integrated circuits are formed from semiconductor substrates within and upon whose surfaces are formed resistors, transistors, diodes and other electrical circuit elements. The electrical circuit elements are connected internally and externally to the semiconductor substrate upon which they are formed through patterned conductor layers which are separated by dielectric layers.
When forming electrical circuit elements within integrated circuits, it is common in the art of integrated circuit fabrication to etch sequentially through multiple integrated circuit layers to form within integrated circuits patterned multi-layer integrated circuit structures employed within electrical cit elements within those integrated circuits. More particularly, it is common in the art of field effect transistor (FET) fabrication within integrated circuits to form patterned polysilicon or polycide gate electrode structures with self-aligned dielectric cap layers within those field effect transistors (FETs). While it is desirable in the art of integrated circuit fabrication to form patterned multi-layer integrated circuit structures, such as but not limited to patterned polysilicon or polycide gate electrode structures with self-aligned dielectric cap layers within field effect transistors (FETs), such multi-layer integrated circuit structures are not formed entirely without problems within integrated circuits.
In particular, problems which are encountered when forming such patterned multi-layer integrated circuit structures include, but are not limited to: (1) adventitious contamination of various portions of the integrated circuit structures due to adventitious atmospheric exposure when sequentially employing multiple independent etching reactors when forming the patterned multi-layer integrated circuit sutures; and (2) formation of residue layers within patterned multi-layer integrated circuit structures formed upon integrated circuit substrate layers of high topographic variation. A pair of schematic cross-sectional diagrams illustrating the latter of these two problems with respect to forming within an integrated circuit a multi-layer polycide gate electrode is shown in FIG. 1 and FIG. 2.
Shown in FIG. 1 is a semiconductor substrate 10 having formed therein and thereupon a pair of isolation regions 12a and 12b which define an active region of the semiconductor substrate 10. As is illustrated in FIG. 1, each of the isolation regions 12a and 12b has formed therein a cavity 13a or 13b closely adjoining the active region of the semiconductor substrate 10. The cavities 13a and 13b define a "bird's beak" region of the isolation regions 12a and 12b, where the cavities 13a and 13b are typically not readily avoidable when forming the isolation regions 12a and 12b through a thermal oxidation method as is conventional in the art of integrated circuit fabrication.
There is also shown in FIG. 1 a blanket gate dielectric layer 14 formed upon the active region of the semiconductor substrate 10 and a series of four blanket layers formed upon or over the isolation regions 12a and 12b and the blanket gate dielectric layer 14. The four blanket layers include: (1) a blanket polysilicon layer 16 formed upon the blanket gate dielectric layer 14 and the isolation regions 12a and 12b; (2) a blanket metal silicide layer 18 formed upon the blanket polysilicon layer 16; (3) a blanket cap dielectric layer 20 formed upon the blanket metal silicide layer 18; and (4) a blanket anti-reflective coating (ARC) layer 22 formed upon the blanket cap dielectric layer 20. Finally, there is shown in FIG. 1 a series of three patterned photoresist layers 24a, 24b and 24c which in the aggregate form a photoresist etch mask layer employed in forming from the series of four blanket layers a gate electrode structure over the active region of the semiconductor substrate 10 and a pair of interconnect structures upon the pair of isolation regions 12a and 12b.
Referring now to FIG. 2, there is shown a schematic cross-sectional diagram illustrating the results of further processing of the integrated circuit whose schematic cross-sectional diagram is illustrated in FIG. 1. Shown in FIG. 2 is the results of sequentially patterning the series of four blanket layers as shown in FIG. 1 to form the gate electrode structure 26b upon the active region of the semiconductor substrate 10 and the pair of interconnect structures 26a and 26c upon the corresponding isolation regions 12a and 12b.
When forming from the integrated circuit whose schematic cross-sectional diagram is illustrated in FIG. 1 the integrated circuit whose schematic cross-sectional diagram is illustrated in FIG. 2, there is typically formed within each cavity 13a or 13b a corresponding patterned polysilicon layer residue 16d or 16e, as illustrated in FIG. 2. The patterned polysilicon layer residues 16d and 16e typically result from either incomplete or shadowed etching of the polysilicon layer 16. Although not specifically illustrated within the schematic cross-sectional diagrams of FIG. 1 and FIG. 2, the blanket anti-reflective coating (ARC) layer 22 and the blanket cap dielectric layer 20 are typically etched through a first reactive ion etch (RIE) method optimized to etch the blanket cap dielectric layer 20, while the blanket metal silicide layer 18 and the blanket polysilicon layer 16 are typically etched through an independent second reactive ion etch (RIE) method optimized to etch the blanket polysilicon layer 16. The selective optimization of the first reactive ion etch (RIE) method for the blanket cap dielectric layer 20 and the second reactive ion etch (RIE) method for the blanket polysilicon layer 16 presumably contributes to formation of the patterned polysilicon layer residues 16d and 16e. Polysilicon layer residues, such as the patterned polysilicon layer residues 16d and 16e, are undesirable within integrated circuit fabrication since they may compromise the functionality or reliability of an integrated circuit within which they are formed.
It is thus in general towards forming within integrated circuits patterned polysilicon layers upon topographic substrate layers while avoiding forming patterned polysilicon layer residues upon the topographic substrate layers that the present invention is generally directed.
Various novel methods for patterning and etching integrated circuit layers within integrated circuits have been disclosed within the art of integrated circuit fabrication. For example, Groechel et al., in U.S. Pat. No. 5,021,121, discloses a method for etching with high selectivity with respect to a silicon substrate layer a via with nearly vertical sidewalls through a silicon oxide dielectric layer formed upon the silicon substrate layer. The method employs specific flow rates of an inert gas, tri-fluoromethane and carbon tetrafluoride.
In addition, Lai, in U.S. Pat. No. 5,188,980, discloses a method for etching, without undercutting, a tungsten silicide polycide gate electrode within a field effect transistor (FET) within an integrated circuit. The method employs a first mixture of chlorine and helium when etching the tungsten silicide layer within the tungsten silicide polycide gate electrode, followed by a helium purge prior to employing a second mixture of chlorine and helium when etching the polysilicon layer within the tungsten silicide polycide gate electrode.
Finally, Roman et al., in U.S. Pat. No. 5,378,659, discloses a method for forming, without reflective notching, an integrated circuit pattern upon a semiconductor substrate. The method employs an anti-reflective layer formed of silicon rich silicon nitride formed beneath a photoresist layer employed in defining the integrated circuit pattern
Desirable in the art are additional methods for forming within integrated circuits patterned layers, such as patterned polysilicon layers. More particularly desirable in the art are additional methods for forming patterned polysilicon layers upon topographic substrate layers within integrated circuits without forming patterned polysilicon layer residues upon the topographic substrate layers. Most particularly desirable in the art are additional methods for forming within integrated circuits multi-layer patterned polysilicon layer containing integrated circuit structures upon topographic substrate layers within integrated circuits without forming patterned polysilicon layer residues upon the topographic substrate layers. It is towards these goals that the present invention is more specifically directed.